1. Field of the Invention
This invention relates in general to methods for manufacturing integrated circuit (IC) devices. More specifically, the invention relates to non-lot based IC device manufacturing methods in which individual devices can be uniquely identified during their assembly, which enables individual tracking of the devices through assembly and, in turn, enables assembly of the devices in a substantially continuous manner.
2. State of the Art
As shown in FIG. 1, a process 10 for manufacturing integrated circuit (IC) devices typically begins with ICs being fabricated on the surfaces of wafers 12 of semiconductor material, such as silicon. Less typically, ICs may also be formed in layers of silicon deposited on layers of sapphire known as Silicon-on-Sapphire (SOS), Silicon-on-Insulator (SOI), or Silicon-on-Glass (SOG).
Once fabricated, ICs are electronically probed to determine whether they are functional (i.e., “good”) or nonfunctional (i.e., “bad”). A computer then stores electronic wafer maps 14 of the wafers 12 identifying the locations of the good and bad ICs on the wafers 12.
After being probed, ICs are sawed from their wafers 12 into discrete IC dice (also known as “chips”) using high-speed precision dicing equipment. IC dice identified as good by their wafer maps 14 are then each “picked” by automated equipment from their sawed wafers 12 and “placed” on an epoxy coated bonding site of one of a set of lead frames 16, while IC dice identified as bad are discarded into a scrap bin 18. The epoxy attaching the good IC dice to their lead frames 16 is allowed to cure, and the attached dice are then wire bonded to their lead frames 16 using high speed bonding equipment. At this point in the process 10, the lead frames 16 of IC dice are still interconnected.
Once wire bonded, IC dice and their lead frames 16 are formed into IC packages using a hot thermosetting plastic encapsulant injected into a mold. Leads of the lead frames 16 project from the IC packages after encapsulation, and these leads are dipped in a cleansing chemical bath in a process referred to as “de-flash.” After de-flash, IC packages are cured to set their plastic encapsulant, and their projecting leads are then electroplated with a lead/tin finish.
After lead finishing, connections between the lead frames 16 of different IC packages are cut to “singulate” the IC packages into discrete IC devices, and the leads projecting from each IC device are then trimmed and formed into their final form. The IC devices are then tested in a simple electronic test that checks for “opens” (i.e., no connection) in the devices where connections should exist and “shorts” (i.e., a connection) where connections should not exist. Devices that fail the opens/shorts test are discarded into the scrap bin 18, and devices that pass proceed to extensive back-end test procedures where they are tested for functionality before being shipped to customers.
ICs are typically tracked by lot number through the fabrication, probe, assembly, and back-end test steps described above so the location of particular lots of ICs within the manufacturing process 10 can be determined. Lot numbers are first assigned to ICs when they are fabricated on semiconductor wafers 12. Typically, a group of 20–50 wafers 12 receives a unique lot number (e.g., 36/1/9970). As the group of wafers 12 proceeds to probe, the wafers 12 are typically split into several sub-lots, with each sub-lot being assigned a new lot number (sometimes referred to as a “sub-lot” number) that is a modified form of the group's original lot number (e.g., 36/1/9970/0, 36/1/9970/1, . . . ). As the group continues through the manufacturing process 10, sub-lots are split and re-split for a variety of reasons until the group is typically split into many sub-lots, all having a unique lot number that is a modified form of the group's original lot number.
An example of ICs being tracked through a portion of assembly using lot numbers is shown in FIG. 2. In the example, ICs are first processed on molding equipment to encapsulate them. Once encapsulated, ICs are fed into output carriers 20, each of which has a unique carrier number (e.g., a bar code). The lot numbers of ICs fed into a particular output carrier 20 are stored in association with the carrier number of the carrier 20 in a data store 22, such as a computer memory system. The output carriers 20 containing the encapsulated ICs are then placed on shelves, with the carrier number of each output carrier 20 being stored in the data store 22 in association with a unique shelf number of the shelf on which the output carrier 20 is placed (e.g., by scanning in the bar code of each output carrier 20 and a bar code of the shelf on which it is placed). Later, selected ICs are retrieved by lot from the shelves for processing on de-flash equipment by first identifying the output carriers 20 associated in the data store 22 with the lot number of the selected ICs, then identifying the shelves associated in the data store 22 with the carrier numbers of the identified output carriers 20, and finally retrieving the identified output carriers 20 from the identified shelves for processing.
Unfortunately, the conventional lot-based tracking procedure described above is not as efficient as desired, as is illustrated by FIG. 3. In a typical assembly step 24, a sub-lot (e.g., sub-lot H) is received from an input queue 26 where sub-lots wait to proceed through the assembly step 24. The assembly step 24 may be any step in the IC assembly process of FIG. 1, including, for example, wafer saw, die attach, die cure, wire bond, molding, de-flash, lead finish, trim and form, and opens/shorts testing.
As a sub-lot advances through the assembly step 24, data 28 related to the assembly step 24 is generated. Such data 28 may include, for example: an identification of the processing equipment and the operating personnel for the assembly step 24; information regarding the set-up of the assembly step 24; and the time and date the sub-lot advanced through the assembly step 24.
Once a sub-lot has advanced through the assembly step 24, a process report 30 is manually or automatically generated based on the generated data 28. To associate the process report 30, and hence the data 28, with the ICs in the sub-lot, and thus track the ICs through the assembly step 24, the process report 30 lists the lot number (e.g., “H”) of the ICs in the sub-lot. Typically, the process report 30 (often referred to as a “lot traveler”) also physically accompanies the sub-lot through the remainder of the manufacturing process to ensure that the data 28 is correlated with the ICs in the sub-lot.
With the process report 30 generated, a processed sub-lot (e.g., sub-lot H) is cleared from equipment associated with the assembly step 24 to an output queue 32 to prepare the assembly step 24 for processing the next sub-lot (e.g., sub-lot I). Once the processed sub-lot is cleared, the next sub-lot can be processed. This “clearing” process is necessary because if two sub-lots (e.g., sub-lots H and I) proceed through the assembly step 24 in a continuous manner, the conventional lot-based tracking procedure described above is unable to correlate the data 28 and the process report 30 generated as each of the two sub-lots proceeds with the correct sub-lot. Instead, the data 28 for the two sub-lots is mixed, causing the conventional tracking procedure to fail to uniquely track the two sub-lots through the assembly step 24.
Thus, the described conventional lot-based tracking procedure is inefficient because it makes inefficient use of often very expensive manufacturing equipment and other resources by leaving sub-lots “parked” in input queues while process reports are generated and the equipment is cleared of already processed sub-lots. In assembly steps which use multiple machines in parallel to process a sub-lot (e.g., wire bond), some machines may be idle while other machines finish their allotment from the sub-lot being processed and the next sub-lot waits in an input queue. In addition, generation of the process reports, as well as clearing a processed sub-lot from equipment, often requires laborious manual work by operating personnel. Also, the conventional tracking procedure is not as reliable as desired, because the process reports that must physically accompany sub-lots through the manufacturing process can be lost or damaged.
As described in U.S. Pat. Nos. 5,301,143, 5,294,812, and 5,103,166, some non-lot based methods have been devised to aid quality control personnel in tracking ICs undergoing failure analysis back to the wafer from which they come. By tracking the ICs back to their wafer, test data related to the ICs can be correlated to the wafer to pinpoint possible problems with the wafer. Such methods take place off the manufacturing line, and involve the use of electrically retrievable identification (ID) codes, such as so-called “fuse ID's,” programmed into individual ICs to identify the ICs. Fuse ID's and other electrically retrievable ID codes are typically programmed into ICs by blowing selected fuses or anti-fuses in circuitry on the ICs so that the circuitry outputs the ID code when accessed. Unfortunately, none of these methods addresses the inefficiency and reliability problems associated with the conventional lot-based tracking procedure described above.
Therefore, there is a need in the art for a non-lot based procedure for tracking ICs through an IC assembly process that uses manufacturing resources more efficiently. Such a procedure should not leave equipment idle while ICs wait to be processed. In addition, such a procedure should achieve a level of reliability not reached by conventional tracking procedures.